Toni December 29, March 29, Datasheet , Download. Complete specifications are provided in the form of data sheets. In addition, a Product Selector Guide and a Handling and Design Guidelines chapter have been included to familiarize the user with these circuits. Download PDF. This website uses cookies so that we can provide you with the best user experience possible. Cookie information is stored in your browser and performs functions such as recognising you when you return to our website and helping our team to understand which sections of the website you find most interesting and useful.
Strictly Necessary Cookie should be enabled at all times so that we can save your preferences for cookie settings. I have tried to be logically consistent so the term I have used describes the pin's function when high true. For example 'disable clock' on the is often labelled 'clock enable' but this can be confusing because it enables the clock when low false. An input described as 'active low' is like this, it performs its function when low.
If you see a line drawn above a label it means it is active low, for example: say 'reset-bar'. Touching a pin while charged with static electricity from your clothes for example may damage the IC! In fact most ICs in regular use are quite tolerant and earthing your hands by touching a metal water pipe or window frame before handling them will be adequate. It is best to build a circuit using just one logic family, but if necessary the different families may be mixed providing the power supply is suitable for all of them.
For example mixing and 74HC requires the power supply to be in the range 3 to 6V. A 74LS output cannot reliably drive a or 74HC input unless a 'pull-up' resistor of 2. For tables showing characteristics of the logic families see: Logic ICs. Driving or 74HC inputs from a 74LS output using a pull-up resistor. The has Schmitt trigger inputs to provide good noise immunity. They are ideal for slowly changing or noisy signals. The hysteresis is about 0.
This gate has a propagation time which is about 10 times longer than normal so it is not suitable for high speed circuits. The gate output is sufficient to drive four 74LS inputs. The count advances as the clock input becomes high on the rising-edge. Each output Q0-Q9 goes high in turn as counting advances.
For some functions such as flash sequences outputs may be combined using diodes. The reset input should be low 0V for normal operation counting When high it resets the count to zero Q0 high. Counting to less than 9 is achieved by connecting the relevant output Q0-Q9 to reset, for example to count 0,1,2,3 connect Q4 to reset. The disable input should be low 0V for normal operation. When high it disables counting so that clock pulses are ignored and the count is kept constant.
It can be used to drive the clock input of another to count the tens. The outputs a-g go high to light the appropriate segments of a common-cathode 7-segment display as the count advances. The maximum output current is about 1mA with a 4. This is sufficient to directly drive many 7-segment LED displays. The table below shows the segment sequence in detail.
When high it resets the count to zero. The disable clock input should be low 0V for normal operation. When low it makes outputs a-g low, giving a blank display. The enable out follows this input but with a brief delay. It can be used to drive the clock input of another to provide multi-digit counting. The is a synchronous counter so its outputs change precisely together on each clock pulse.
This is helpful if you need to connect the outputs to logic gates because it avoids the glitches which occur with ripple counters.
The count occurs as the clock input becomes high on the rising-edge. For normal operation counting preset , and carry in should be low. The counter may be preset by placing the desired binary number on the inputs A-D and briefly making the preset input high. There is no reset input, but preset can be used to reset the count to zero if inputs A-D are all low. Please see below for details of connecting synchronous counters like the in a chain.
These are synchronous counters so their outputs change precisely together on each clock pulse. This is helpful if you need to connect their outputs to logic gates because it avoids the glitches which occur with ripple counters.
For normal operation counting preset , reset and carry in should be low. When reset is high it resets the count to zero , QA-QD low. The clock input should be low when resetting.
The counter may be preset by placing the desired binary number on the inputs A-D and briefly making the preset input high, the clock input should be low when this happens. Please see below for details of connecting synchronous counters like the and in a chain. The diagram below shows how to link synchronous counters. Notice how all the clock CK inputs are linked. Carry out CO feeds carry in CI of the next counter. Carry in CI of the first counter should be low for , and counters. Normally a clock signal is connected to the clock input, with the enable input held high.
Counting advances as the clock signal becomes high on the rising-edge. For normal operation the reset input should be low, making it high resets the counter to zero , QA-QD low. Counting to less than the maximum 9 or 15 can be achieved by connecting the appropriate output s to the reset input, using an AND gate if necessary.
The diagram below shows how to link and counters. Notice how the normal clock inputs are held low, with the enable inputs being used instead. With this arrangement counting advances as the enable input becomes low on the falling-edge allowing output QD to supply a clock signal to the next counter. The complete chain is a ripple counter, although the individual counters are synchronous! The is a ripple counter so beware that glitches may occur in any logic gate systems connected to its outputs due to the slight delay before the later counter outputs respond to a clock pulse.
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